29/01/2014 Developmental Update

Greetings Miners!

Engineering updates for this week:

  1. Host board will be a two board solution ( SOM & Daughter board).
  2. Wifi capability has been added to the host board.
  3. Power measurement capability added to the host board.
  4. Temperature measurement capability added to the mining board.
  5. ASIC – Physical design is going on
    1. Memory cells are chosen as array of 1024*128 bits.
    2. Various options for memory floor planning is being tried upon like multiple memories being stacked on top of each other along with grouping them together for better die size.
  6. RTL synthesis has been tried out with HVT , RVT and LVT cells. LVT offers good frequency, however power leakage is higher, RVT offers balance on timing and power.
  7. Block level pin assignments in progress.
  8. DFT Scan insertion in progress.
  9. Place and route in progress.