Engineering updates for this week:
- Host board will be a two board solution ( SOM & Daughter board).
- Wifi capability has been added to the host board.
- Power measurement capability added to the host board.
- Temperature measurement capability added to the mining board.
- ASIC – Physical design is going on
- Memory cells are chosen as array of 1024*128 bits.
- Various options for memory floor planning is being tried upon like multiple memories being stacked on top of each other along with grouping them together for better die size.
- RTL synthesis has been tried out with HVT , RVT and LVT cells. LVT offers good frequency, however power leakage is higher, RVT offers balance on timing and power.
- Block level pin assignments in progress.
- DFT Scan insertion in progress.
- Place and route in progress.