We have been able to get the scrypt algorithm working in FPGA. However, after further analysis we realised that FPGA is not the correct platform for this algorithm in terms of high-speed hashrate, it is possible however not financially or efficiently viable. This is primarily, because of the design of the scrypt algorithm, there are few loops which require a lot of memory and all operations have to be sequential which cannot be made parallel, so you will not be able to get high speeds. The algorithm was designed in this way to avoid hacking.
The problem with FPGA is that it cannot work at very high frequency. An example is we have seen 800 Mhz in Zynq series. The fastest memory available to an FPGA is on itself which is the block ram. And that we don't have in abundance. This is something which is present in GPU boards though.
You need to physically implement the algorithm on an FPGA in order to actually see how in depth the algorithm works, simulations are not enough. So our efforts have been beneficial in order to come up with a better method of scrypt hashing. We will be releasing a full analysis report as a proof of concept of the algorithm on an FPGA anyway in the near future.
The implementation has been beneficial to us as a team and most importantly our well established partners, in order to get fully familiar with the algorithm itself. So it has given us an in depth knowledge in our new design to overcome the limitations of an FPGA in this case. (will be disclosing who our partners are after our official press releases).
Therefore, We believe the demand is high enough to go ahead with this. We are working on a fabric based on a GPGPU design, as the only way to speed up a sequential algorithm is by overclocking or choosing a fabric which can run at very high speeds and has got lots of memory. As GPGPU implementations have different syntaxes than that of FPGA's, we will be taking advantage of our partner's expertise and connections in manufacturing in this area.
Not only is this a better high speed choice as an end product for miners, it is also business wise for us as we can take advantage of economies of scale, and lower cost per unit therefore lower price for the customers (FPGA's are much more expensive). Our actual design will be reaching speeds in the 1000s Kilohashes/second.
We are in early development and much more information will be coming soon. For now visit our website or follow us on twitter for early development updates.